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gnucap:user:netlist_import_and_export [2024/07/09 21:24]
aldavis [Verilog attributes]
gnucap:user:netlist_import_and_export [2024/07/17 01:29] (current)
aldavis [Hierarchy]
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     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .pn(b3));     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .pn(b3));
      
-    net a (.1(a0).2(a1)); +    net a (a0, a1); 
-    net b (.1(b1).2(b2).3(b3)); +    net b (b1, b2, b3); 
-    net c (.1(c0).2(c2).3(c3));+    net c (c0, c2, c3);
   endmodule   endmodule
  
-We have replaced the nodes with nets, which are now first class objects.+We have replaced the nodes with nets, which are now first class objects.   This will give us a way to represent the interconnect in a schematic drawing or a layout.  It also provides essential data to support analysis and simulation of the interconnect. 
  
 Looking at net "b" as an example, it has 3 connections : r1 pin n, p2 pin p, and u1 pin pn. Looking at net "b" as an example, it has 3 connections : r1 pin n, p2 pin p, and u1 pin pn.
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 ==== Adding physical position ==== ==== Adding physical position ====
  
-Now we use the attributes to specify the location.  All positions indicate place where a connection is madeor could be made.  Then the positions of things that connect there can be determined.  I am thinking schematic for nowbut the same concept applies to layout.  It is not necessary to place all of the nodes because others can be impliedbut you could as a check or to imply flip and rotate.  If they are inconsistentrubberbanding would preserve connectivity Usuallyyou can place one node per component, and let the nets floatexcept that you could add extra nodes to nets so you can place junctions.+Now we use the attributes to specify the location.  We need to locate the various objects.  In most cases, we need to specify some point of every object that will identify its location.  Some programs use some notion of "center"which is ambiguous.  We will use the electrical connection points, often called "pins", as the location points for things that have an electrical connection.  For objects that do not have electrical connections, reference points can be used. 
 + 
 +We will number the pins, by position, 0, 1, 2, ...  Then we use x0,y0, and so on to locate them.  Usually one of them is adequate to locate an object.  The others can "float"allowing the actual location to be determined by the surroundings.  It is permissible to overspecify locations, provided they are self-consistentand consistent with connections. 
 + 
 +In addition to the positionshflip, vflip, and angle are supported.  If there is both a flip and an angleflip will be done first, then angle. 
 + 
 +Another attribute named for the specific tool (example: S0_geda) can be used to stash tool specific data that doesn't fit otherwise.  This is intended to assist with a translation from this format back to the tool format.  Normally, this would be a string containing a composite of the info (S0_geda="5 10 0 0 0 0 1")  If more than one string in a scope is needed, suffixes can be used. (S0_geda_color="blue" S0_geda_symbol="resistor-1.sym")  These are stored and passed on without any interpretation.
  
   module amp (.a(a0), .c(c0));   module amp (.a(a0), .c(c0));
-    (* S0_x1=-5m, S0_y1=0m *)  input a0; +    (* S0_x0=-5m, S0_y0=0m *)  input a0; 
-    (* S0_x1=30m, S0_y1=-3m *) output c0;+    (* S0_x0=30m, S0_y0=-3m *) output c0;
      
-    (* S0_x1=0m,  S0_y1=0m *)  resistor #(.r(1k))      r1 (.p(a1), .n(b1)); +    (* S0_x0=0m,  S0_y0=0m *)  resistor #(.r(1k))      r1 (.p(a1), .n(b1)); 
-    (* S0_x1=24m, S0_y1=7m *)  resistor #(.r(1k))      r2 (.p(b2), .n(c2)); +    (* S0_x0=24m, S0_y0=7m *)  resistor #(.r(1k))      r2 (.p(b2), .n(c2)); 
-    (* S0_x1=25m, S0_y1=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));+    (* S0_x0=25m, S0_y0=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
      
-    net a (.1(a0).2(a1)); +    net a (a0, a1); 
-    net b (.1(b1).2(b2).3(b3)); +    net b (b1, b2, b3); 
-    net c (.1(c0).2(c2).3(c3));+    net c (c0, c2, c3);
   endmodule   endmodule
  
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     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
      
-    (* S0_x1=-5m, S0_y1=0m,  S0_x2=0m,  S0_y2=0m *)  net a (.1(a0).2(a1)); +    (* S0_x0=-5m, S0_y0=0m,  S0_x1=0m,  S0_y1=0m *)  net a (a0, a1); 
-    (* S0_x2=24m, S0_y2=7m *)                        net b (.1(b1).2(b2).3(b3)); +    (* S0_x1=24m, S0_y1=7m *)                        net b (b1, b2, b3); 
-    (* S0_x1=30m, S0_y1=-3m, S0_x3=25m, S0_y3=-3m *) net c (.1(c0).2(c2).3(c3));+    (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m *) net c (c0, c2, c3);
   endmodule   endmodule
 +  
 +This one is overdetermined, but legal, and produces the same result.
  
-Any reference to node can be located:+  module amp (.a(a0), .c(c0)); 
 +    (* S0_x0=-5m, S0_y0=0m *)  input a0; 
 +    (* S0_x0=30m, S0_y0=-3m *) output c0; 
 +   
 +    (* S0_x0=0m,  S0_y0=0m *)  resistor #(.r(1k))      r1 (.p(a1), .n(b1)); 
 +    (* S0_x0=24m, S0_y0=7m *)  resistor #(.r(1k))      r2 (.p(b2), .n(c2)); 
 +    (* S0_x0=25m, S0_y0=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3)); 
 +   
 +    (* S0_x0=-5m, S0_y0=0m,  S0_x1=0m,  S0_y1=0m *)  net a (a0, a1); 
 +    (* S0_x1=24m, S0_y1=7m *)                        net b (b1, b2, b3); 
 +    (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m *) net c (c0, c2, c3); 
 +  endmodule 
 +   
 + 
 +==== Multiple applications, both layout and schematic ==== 
 + 
 +Files can be combined.  
  
   module amp (.a(a0), .c(c0));   module amp (.a(a0), .c(c0));
     input a0;     input a0;
     output c0;     output c0;
-     +  
-    (* S0_x1=-5m, S0_y1=0m *)  electrical a0; +
-    (* S0_x1=30m, S0_y1=-3m *) electrical c0; +
-    (* S0_x1=0m,  S0_y1=0m *)  electrical a1; +
-    (* S0_x1=24m, S0_y1=7m *)  electrical b2; +
-    (* S0_x1=25m, S0_y1=-3m *) electrical c3; +
     resistor #(.r(1k))      r1 (.p(a1), .n(b1));     resistor #(.r(1k))      r1 (.p(a1), .n(b1));
     resistor #(.r(1k))      r2 (.p(b2), .n(c2));     resistor #(.r(1k))      r2 (.p(b2), .n(c2));
     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));     opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
      
-    net a (.1(a0).2(a1)); +    (* S0_x0=-5m, S0_y0=0m,  S0_x1=0m,  S0_y1=0m,  PC0_x0=-5m, PC0_y0=0m,  PC0_x1=0m,  PC0_y1=0m *)  net a (a0, a1); 
-    net b (.1(b1).2(b2).3(b3)); +    (* S0_x1=24m, S0_y1=7m *)                   (* PC0_x1=24m, PC0_y1=7m *)                          net b (b1, b2, b3); 
-    net c (.1(c0).2(c2).3(c3));+    (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m, PC0_x0=30m, PC0_y0=-3m, PC0_x2=25m, PC0_y2=-3m *) net c (c0, c2, c3);
   endmodule   endmodule
- +  
- +
- +
- +
-==== Multiple applications, both layout and schematic ====+
  
 Portions that apply in only certain contexts can be selectively included with 'ifdef: Portions that apply in only certain contexts can be selectively included with 'ifdef:
  
   module amp (.a(a0), .c(c0));   module amp (.a(a0), .c(c0));
-    resistor #(.r(1k)) r1 (.p(a1), .n(b1))+    input a0
-    resistor #(.r(1k)) r2 (.p(b2), .n(c2)); +    output c0;
-    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .pn(b3));+
      
-    net a (.1(a0).2(a1)); +    resistor #(.r(1k))      r1 (.p(a1), .n(b1)); 
-    net b (.1(b1).2(b2), .3(b3)); +    resistor #(.r(1k))      r2 (.p(b2), .n(c2)); 
-    net c (.1(c0), .2(c2), .3(c3));+    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3));
      
   `ifdef SCHEMATIC   `ifdef SCHEMATIC
-    place #(.$xposition(24m).$yposition(7m))  place_b2 (b2); +    (* S0_x0=-5mS0_y0=0m,  S0_x1=0m,  S0_y1=0m *)  net a (a0, a1); 
-    place #(.$xposition(0m) .$yposition(0m))  place_a1 (a1); +    (* S0_x1=24mS0_y1=7m *                       net b (b1, b2, b3); 
-    place #(.$xposition(25m).$yposition(-3m)) place_c3 (c3);+    (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m *net c (c0, c2, c3);
   `endif   `endif
-  `ifdef LAYOUT +  `ifdef LAYOUT     
-    place #(.$xposition(1000u).$yposition(0u)) place_b2 (b2); +    (* PC0_x0=-5mPC0_y0=0m,  PC0_x1=0m,  PC0_y1=0m * net a (a0, a1); 
-    place #(.$xposition(0m)   .$yposition(0u)) place_a1 (a1); +    (* PC0_x1=24mPC0_y1=7m *                         net b (b1, b2, b3); 
-    place #(.$xposition(2000u).$yposition(0u)) place_c3 (c3);+    (* PC0_x0=30m, PC0_y0=-3m, PC0_x2=25mPC0_y2=-3m *net c (c0, c2, c3);
   `endif   `endif
   endmodule   endmodule
 +  
  
 ==== Mapping to the application ==== ==== Mapping to the application ====
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 ==== Complex nets can be encapsulated ==== ==== Complex nets can be encapsulated ====
  
-  module net23842 (1,2,3); +  module net23842 (1,2,3,4); 
-    net n23482 (1,2);+    net n23482 (1,2,4);
     net n84333 (2,3);     net n84333 (2,3);
-    `ifdef SCHEMATIC 
-      place ... 
-      place ... 
-      place ... 
-    `endif 
   endmodule   endmodule
  
-  module net9393 (1,2); 
-    net #(.color(blue), .thickness(thin)) n38423 (1,2); 
-  endmodule 
  
-==== Hierarchy ==== 
- 
-The system supports hierarchy. 
- 
-  module twoamps (in, out); 
-    amp a1 (in, mid1); 
-    amp a2 (mid2, out); 
-    net mid (mid1, mid2); 
-  'ifdef SCHEMATIC 
-    place #(.$xposition(0),   .$yposition(0)) place_in  (in); 
-    place #(.$xposition(30m), .$yposition(0)) place_mid (mid2); 
-  'endif 
-  endmodule 
gnucap/user/netlist_import_and_export.1720578250.txt.gz · Last modified: 2024/07/09 21:24 by aldavis
 
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