*http://11.gnucap.org/dokuwiki/2024-03-28T08:10:09-05:00FeedCreator 1.7.2-ppt DokuWikignucap:start - add chat2024-02-27T05:41:53-05:002024-02-27T05:41:53-05:002024-02-27T05:41:53-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:start?rev=1709034113&do=difffelixsGnucap is the GNU Circuit Analysis Package
Gnucap is a modern post-spice circuit simulator with several advantages over Spice derivatives.
* About Gnucap, the sales pitch
* Old web site
* Mailing lists
* Chat
* Download:
* Latest stable release
* Current development versiongnucap:chat - created2024-02-27T05:40:35-05:002024-02-27T05:40:35-05:002024-02-27T05:40:35-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:chat?rev=1709034035&do=difffelixsThere is a chat on matrix, #gnucap:matrix.org.
It's a starting point, checking the need. Feel free to suggest or provide alternatives.gnucap:nix_on_debian - add alternative to build, formatting2024-02-22T05:03:25-05:002024-02-22T05:03:25-05:002024-02-22T05:03:25-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:nix_on_debian?rev=1708599805&do=difffelixsWalkthrough: Gnucap on Nix on Debian
(root)# apt install nix-bin
It may be required to set up nix manually.
(user)[~]$ mkdir -p .local/share/nix/root/nix
(root)# mount -o bind ~user/.local/share/nix/root/nix/ /nix
The package description is in a git repo hosted on github.
(TODO: find mirror.)gnucap:packaging - add nix package2024-02-21T05:16:28-05:002024-02-21T05:16:28-05:002024-02-21T05:16:28-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:packaging?rev=1708514188&do=difffelixs* arch linux
* user repository
* debian
* available packages
* team repositories
* build manually
* gentoo
* status page
* nix
* package repo
* nix_on_debiangnucap:manual:build - reference distro packages summary2024-02-21T05:12:24-05:002024-02-21T05:12:24-05:002024-02-21T05:12:24-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:build?rev=1708513944&do=difffelixsInstallation
* The easy way
* The old easy way
* If that doesn't work
* Details, custom compilation
* other build systems
* distro packagesgnucap:manual:autotools - add 20240205 tarball2024-02-10T03:39:09-05:002024-02-10T03:39:09-05:002024-02-10T03:39:09-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:autotools?rev=1707557949&do=difffelixsBuild Gnucap with foreign build systems
Building a program boils down to compiling binaries from source code using a compiler. However, an large number of “build systems” has been invented for the purpose of invoking a compiler and managing the data. Such build systems are necessarily bound to tradeoffs between simplicity and fancyness driven by both taste and policies. Good tradeoffs do not seem to exist yet. The high number of different implementations displays the lack of agreement on best p…gnucap:manual:modelgen-verilog - more links2024-01-30T11:58:49-05:002024-01-30T11:58:49-05:002024-01-30T11:58:49-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:modelgen-verilog?rev=1706637529&do=difffelixsman page below, for now, see repo for current version. Relevant project page.
Modelgen-verilog implementation notes are here.
GNUCAP-MG-VAMS(1) Gnucap Modelgen GNUCAP-MG-VAMS(1)
NAME
gnucap-mg-vams - GNU Circuit Analysis Package .vams translator
SYNOPSIS
gnucap-mg-vams { [OPTIONS] [ACTIONS] }
DESCRIPTION
Gnucap-Modelgen is a translator tool in the Gnucap suite. It will
transform Verilog-AMS models into C++ code implementing Gnucap com‐
…gnucap:manual:languages:verilog - lang_verilog now in mgsim2024-01-30T11:47:12-05:002024-01-30T11:47:12-05:002024-01-30T11:47:12-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:languages:verilog?rev=1706636832&do=difffelixsThe Verilog language plugin attempts to support the syntax of the Verilog-AMS language.
Not all features of Verilog-AMS are supported, but those that work will work with Verilog-AMS syntax. Wherever possible, Gnucap features will work in Verilog-AMS mode, even if they don't work in Verilog-AMS.gnucap:manual - list modelgen2024-01-21T15:11:37-05:002024-01-21T15:11:37-05:002024-01-21T15:11:37-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual?rev=1705871497&do=difffelixsThis is a draft of the manual for the development version of gnucap.
It attempts to describe the latest development release.
* Introduction
* Commands
* Devices
* Languages
* Modelgen
* How to
* Compatibility
* Tech notes
* Building and Installation
* Examplesgnucap:manual:modelgen - created2024-01-21T15:10:43-05:002024-01-21T15:10:43-05:002024-01-21T15:10:43-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:modelgen?rev=1705871443&do=difffelixsModelgen implements the translation of compact device models to code that can be compiled into a plugin and loaded by the simulator. The traditional version that is currently included with Gnucap reads .model files and writes Gnucap plugins in C++. The version currently under development, Modelgen-Verilog, reads a growing subset of Verilog-AMS, a standardised modelling language.gnucap:manual:tech:modelgen - more branch details2023-12-21T18:02:45-05:002023-12-21T18:02:45-05:002023-12-21T18:02:45-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:tech:modelgen?rev=1703203365&do=difffelixsThe term “modelgen” refers to the device model generator and language that has
been part of the Gnucap project from early on. Modelgen reads device
descriptions and emits C++ code to be compiled into plugins. Support for
Verilog-AMS compact models has been implemented in a modelgen successor,
“modelgen-verilog”, following the design patterns and device architecture.
Major technical advantages of the latter are automatic differentiation and
support for device specific numerical tolerances. Others…gnucap:manual:tech:verilog - section headings2023-12-21T06:16:02-05:002023-12-21T06:16:02-05:002023-12-21T06:16:02-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:tech:verilog?rev=1703160962&do=difffelixsSome Verilog implementation notes
module
A module in a Verilog netlist is a collection of components similar to a SPICE
subcircuit. Like paramsets, modules are declared at top level only. A module
is an object inherited from BASE_SUBCKT, a COMPONENT that permits subdevices.
Type resolution and elaboration is different to SPICE. Verilog has no
“subtypes”: each subdevice refers to a COMPONENT by type name and has
parameters and ports. The type name is resolved after read-in, and held by a
stub …gnucap:manual:tech2023-12-20T19:52:39-05:002023-12-20T19:52:39-05:002023-12-20T19:52:39-05:00http://11.gnucap.org/dokuwiki/doku.php/gnucap:manual:tech?rev=1703123559&do=diffadminThis section describes technical aspects of Gnucap.
Here, you will find information that will help you understand how it works and to extend it.
* How we use git.
* plugins
* modelgen
* testing
* style
* adding models (old)
* old tech notes