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gnucap:manual:tech:verilog [2024/05/05 18:51]
felixs more on paramset
gnucap:manual:tech:verilog [2024/09/17 10:33] (current)
felixs describe transition filter
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 Given a module declaration, the standard does not offer a way to fix a subset of its parameters, while transparently passing through the others. Paramset sort of does it, but not without changing the behaviour of the specialised device relative to the generic one. Typical use cases are devices specialised without noise, without initial conditions, without additional resistors, without temperature, or with their levels fixed (wip...). Given a module declaration, the standard does not offer a way to fix a subset of its parameters, while transparently passing through the others. Paramset sort of does it, but not without changing the behaviour of the specialised device relative to the generic one. Typical use cases are devices specialised without noise, without initial conditions, without additional resistors, without temperature, or with their levels fixed (wip...).
 +
 +===== transition filter =====
 +
 +The LRM description for the transition function is unclear. The situation where
 +a new transition overlaps with another needs clarification. A transition filter
 +holds a waveform, similar to the delay line. It is updated whenever
 +transition is called.
 +
 +In any case, the new waveform must be continuous in all arguments of the
 +new_transition call. Here's how this may be achieved. Suppose, transition is
 +called at time t0, with delay d, new start time ts=t0+d, rise or fall time rf
 +and destination l.
 +
 +If the waveform has a sample at t0, future samples are deleted. 
 +
 +Otherwise, the future samples are deleted, excluding the first one after t0,
 +say td1. Now let s0 be the slope at t0. The case s0=0 is simple, otherwise assume
 +s0>0 w.l.o.g.
 +
 +The sample at td1 has a value v1. This gives rise to a slope ps of (ts, v1),
 +(ts+rf, l). Also, let vs be the value at ts.
 +
 +If ps>s0, we drop the sample at td1 and put in (ts,vs).  Else if v0<l, we
 +compute (ti, vi) the intersection of (ts, v1) -- (ts+rf, l) with the rising
 +edge, and cut it short by moving (ts,vs) to (ti, vi).
 +
 +Finally, put in (ts+rf, l).
gnucap/manual/tech/verilog.1714953074.txt.gz · Last modified: 2024/05/05 18:51 by felixs
 
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