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gnucap:manual:tech:verilog [2022/12/12 12:01] felixs created |
gnucap:manual:tech:verilog [2023/12/21 06:16] (current) felixs section headings |
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| - | === Some Verilog implementation notes === | + | ===== Some Verilog implementation notes ===== |
| - | == module == | + | ==== module ==== |
| A module in a Verilog netlist is a collection of components similar to a SPICE | A module in a Verilog netlist is a collection of components similar to a SPICE | ||
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| permits overloading. In Gnucap any type name can refer to multiple prototypes. | permits overloading. In Gnucap any type name can refer to multiple prototypes. | ||
| - | == paramset == | + | ==== paramset ==== |
| A paramset is a COMPONENT with a named reference to another of an underlying | A paramset is a COMPONENT with a named reference to another of an underlying | ||