SPICE has irregular and confusing syntax. The preferred way to use SPICE netlists is through subckt declarations. A subckt declaration creates a type that can be used in any language. Case sensitivity can be enabled (default is off in Spice), in order to avoid problems later, when the netlist is expanded.

spice
.options noinsensitive
.subcircuit mydev(a, b)
  .parameter r=1
  R1 a b r
.ends

The device above may contain more elaborate models and/or behavioural modeling quirks. An instanciation in Spice will look like

X1 p 0 mydev r=1k

The instanciation in Verilog is possible as follows. Note that verilog is case sensitive.

verilog
mydev #(.r(1k)) my_resistor(p, 0);
vsource #(.v(1)) v1(p, 0);

// these commands are specific to gnucap
print dc v(p) i(my_resistor.R1)
dc

It is generally not required to use Spice netlists or models in Gnucap. When making the transition from Spice, spice2verilog may be useful.